FPGA systolic array AI engine
☆37Jan 2, 2026Updated 6 months ago
Alternatives and similar repositories for tensor_accelerator
Users that are interested in tensor_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 10 months ago
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆17Dec 14, 2025Updated 7 months ago
- ☆15May 24, 2025Updated last year
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 8 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated 5 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Netlist API (and more) for EDA flow development☆149Updated this week
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆15Jun 26, 2024Updated 2 years ago
- ☆79Apr 22, 2025Updated last year
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆20May 5, 2026Updated 2 months ago
- ☆17Feb 15, 2025Updated last year
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆25Jan 24, 2026Updated 5 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A Risc-V SoC for Tiny Tapeout☆55Jul 12, 2026Updated last week
- Demo SoC for SiliconCompiler.☆64Jul 2, 2026Updated 2 weeks ago
- This project is to design yolo AI accelerator in verilog HDL.☆40Jul 3, 2026Updated 2 weeks ago
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 2 years ago
- The LLVM Symbolic Simulator, part of SAW.☆22Jul 17, 2020Updated 6 years ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆19Jul 9, 2026Updated last week
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆68Aug 18, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CATCH 1.0, Initial full release of CATCH cost model.☆19Mar 3, 2026Updated 4 months ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- ☆12Jun 11, 2018Updated 8 years ago
- CVA6 softcore contest☆23Jul 8, 2026Updated last week
- RTL data structure☆69Apr 23, 2026Updated 2 months ago
- ☆21Updated this week
- ☆12May 8, 2022Updated 4 years ago
- ☆42Dec 21, 2025Updated 6 months ago
- A parser for PTX 6.5☆13Jun 19, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Jun 20, 2023Updated 3 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆45Feb 23, 2026Updated 4 months ago
- CamJ: an energy modeling and system-level exploration framework for in-sensor visual computing☆26Sep 29, 2023Updated 2 years ago
- Processor support packages☆22Feb 2, 2021Updated 5 years ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆40Jun 17, 2025Updated last year
- APB master and slave developed in RTL.☆26Oct 25, 2025Updated 8 months ago
- Official implementation of the ICLR'25 paper "QERA: an Analytical Framework for Quantization Error Reconstruction".☆14Feb 4, 2025Updated last year