FPGA systolic array AI engine
☆37Jan 2, 2026Updated 9 months ago
Alternatives and similar repositories for tensor_accelerator
Users that are interested in tensor_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog file list pruner☆19Sep 14, 2026Updated 3 weeks ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Aug 23, 2026Updated last month
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 9 months ago
- ☆15May 24, 2025Updated last year
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 11 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆29Feb 16, 2026Updated 7 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆17Jun 26, 2024Updated 2 years ago
- ☆92Apr 22, 2025Updated last year
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆20Aug 25, 2026Updated last month
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆20Apr 27, 2026Updated 5 months ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆28Jan 24, 2026Updated 8 months ago
- A Risc-V SoC for Tiny Tapeout☆61Jul 12, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This project is to design yolo AI accelerator in verilog HDL.☆45Updated this week
- Demo SoC for SiliconCompiler.☆64Jul 2, 2026Updated 3 months ago
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 2 years ago
- The LLVM Symbolic Simulator, part of SAW.☆22Jul 17, 2020Updated 6 years ago
- Netlist API (and more) for EDA flow development☆165Updated this week
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆22Nov 12, 2025Updated 10 months ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆70Aug 18, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CATCH 1.0, Initial full release of CATCH cost model.☆21Mar 3, 2026Updated 7 months ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- ☆12Jun 11, 2018Updated 8 years ago
- CVA6 softcore contest☆24Jul 8, 2026Updated 3 months ago
- RTL data structure☆69Apr 23, 2026Updated 5 months ago
- ☆23Sep 28, 2026Updated last week
- ☆12May 8, 2022Updated 4 years ago
- ☆43Dec 21, 2025Updated 9 months ago
- A parser for PTX 6.5☆13Jun 19, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆13Jun 20, 2023Updated 3 years ago
- CamJ: an energy modeling and system-level exploration framework for in-sensor visual computing☆27Sep 29, 2023Updated 3 years ago
- ☆22Oct 5, 2024Updated 2 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆51Jul 22, 2026Updated 2 months ago
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆44Aug 25, 2026Updated last month
- Official implementation of the ICLR'25 paper "QERA: an Analytical Framework for Quantization Error Reconstruction".☆14Feb 4, 2025Updated last year
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆10Apr 19, 2020Updated 6 years ago