OpenLayout: an open-source custom IC design environment (KLayout, xschem, ngspice, FasterCap). ASAP7 today, support for more PDKs coming.
☆22Nov 4, 2026Updated last week
Alternatives and similar repositories for OpenLayout
Users that are interested in OpenLayout are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation☆13Apr 30, 2026Updated 6 months ago
- The SoC for the introduction to chip design course spring 2026☆21May 22, 2026Updated 5 months ago
- An analog circuit topology benchmark for LLMs☆17Jun 23, 2026Updated 4 months ago
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆26Jun 14, 2026Updated 4 months ago
- IP forge - discover, fetch and install open PDK IP packages☆13Aug 6, 2026Updated 3 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated last year
- Open-source desktop workspace for IC design — schematic capture, analog optimization, SPICE/RTL simulation, synthesis, and digital implem…☆14Updated this week
- The VE-HEP RTL and Firmware☆12Mar 19, 2024Updated 2 years ago
- The basic tutorial of the interposer design☆12Feb 1, 2019Updated 7 years ago
- A fast, open-source DRC (Design Rule Check) engine for GDSII layouts.☆63Updated this week
- NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enable…☆18Aug 16, 2026Updated 2 months ago
- Native powerpc-apple-darwin8.11.0 gcc and friends.☆13Mar 25, 2025Updated last year
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- DeepSeek Harness (dsh) plugin for comprehensive arXiv literature search, with Jev-powered AI screening and classification.☆15Oct 22, 2026Updated 3 weeks ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Nature Figure 可编辑版:科研图同步输出 SVG 与原生可编辑 PPT,打开即可逐元素修改。☆91Oct 13, 2026Updated 3 weeks ago
- [Interspeech 2024] Official implementation of "ED-sKWS: Early-Decision Spiking Neural Networks for Rapid,and Energy-Efficient Keyword Spo…☆12Nov 22, 2024Updated last year
- ☆14Apr 29, 2024Updated 2 years ago
- Digital logic benchmark suite☆96Nov 3, 2026Updated last week
- Digital Design Equivalence Checking☆120Updated this week
- RISC-V SoC — Complete RTL-to-GDSII Flow (SKY130 130nm) | 34 Hardened Modules | 107K+ Gates☆27May 17, 2026Updated 5 months ago
- Open-source compiler that hardwires LLM weights into mask-programmed compute-in-ROM silicon on open PDKs☆48Nov 6, 2026Updated last week
- ☆22Oct 5, 2024Updated 2 years ago
- ☆10Mar 28, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.☆32Updated this week
- Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations☆14Jan 22, 2020Updated 6 years ago
- ☆11Sep 8, 2021Updated 5 years ago
- ☆21Nov 2, 2026Updated last week
- CoreSmith is a Prompt to GDS Agentic Flow☆51Oct 29, 2026Updated 2 weeks ago
- Blender GDSII Importer with PDK Support☆142Oct 16, 2026Updated 3 weeks ago
- ☆48Oct 25, 2026Updated 2 weeks ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated 3 weeks ago
- Full pipeline for building LLM, including pretrain, instruction tuning with RLHF, DPO, and distillation☆15Aug 14, 2026Updated 2 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A modular hardware abstraction library☆53Nov 2, 2026Updated last week
- ☆42Oct 16, 2026Updated 3 weeks ago
- ☆23Updated this week
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- CXLMemUring: A Hardware Software Co-design Paradigm for Asynchronous and Flexible Parallel CXL Memory Pool Access☆13Sep 13, 2026Updated 2 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated 2 years ago
- Neural-Ordinary-Differential-Equations 🌟 Star if you like it! 🌟☆11Jun 22, 2026Updated 4 months ago
Are these results useful?