useredsa / MBPlib
☆15Updated last week
Related projects ⓘ
Alternatives and complementary repositories for MBPlib
- high-performance RTL simulator☆139Updated 4 months ago
- RiVEC Bencmark Suite☆104Updated last week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆61Updated this week
- Unit tests generator for RVV 1.0☆59Updated 3 weeks ago
- The University of Bristol HPC Simulation Engine☆93Updated this week
- Modeling Architectural Platform☆167Updated this week
- The Sniper Multi-Core Simulator☆100Updated last week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆86Updated last week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- ☆86Updated 8 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆24Updated this week
- Benchmarks for Accelerator Design and Customized Architectures☆115Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- ☆36Updated 7 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆135Updated this week
- CGRA Compilation Framework☆81Updated last year
- ILA Model Database☆20Updated 4 years ago
- Vector Acceleration IP core for RISC-V*☆148Updated this week
- A scalable High-Level Synthesis framework on MLIR☆228Updated 5 months ago
- Chisel RISC-V Vector 1.0 Implementation☆50Updated this week
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆237Updated 4 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆46Updated 3 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆12Updated 2 years ago
- ☆84Updated 9 months ago
- A dynamic verification library for Chisel.☆140Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated last month
- Branch Predictor Optimization for BlackParrot☆13Updated 7 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆155Updated this week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆79Updated 7 months ago