useredsa / MBPlibLinks
☆18Updated last year
Alternatives and similar repositories for MBPlib
Users that are interested in MBPlib are comparing it to the libraries listed below
Sorting:
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆155Updated this week
- high-performance RTL simulator☆184Updated last year
- Championship Branch Prediction 2025☆67Updated 7 months ago
- RiVEC Bencmark Suite☆126Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆137Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆125Updated 3 months ago
- The University of Bristol HPC Simulation Engine☆104Updated 4 months ago
- Unit tests generator for RVV 1.0☆98Updated last month
- Qemu tracing plugin using SimPoints☆17Updated last year
- The Task Parallel System Composer (TaPaSCo)☆116Updated 2 weeks ago
- ☆108Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆56Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆43Updated 11 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- Modeling Architectural Platform☆215Updated last week
- gem5 configuration for intel's skylake micro-architecture☆53Updated 4 years ago
- ☆39Updated 2 months ago
- Implementation of TAGE Branch Predictor - currently considered state of the art☆52Updated 11 years ago
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- Open-source RTL logic simulator with CUDA acceleration☆247Updated 3 months ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 3 months ago
- The Sniper Multi-Core Simulator☆162Updated 2 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆194Updated this week
- Microprobe: Microbenchmark generation framework☆24Updated 3 months ago
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated last year
- ☆52Updated 11 months ago