KanPard005 / RISCY_V_TAGELinks
☆12Updated 4 years ago
Alternatives and similar repositories for RISCY_V_TAGE
Users that are interested in RISCY_V_TAGE are comparing it to the libraries listed below
Sorting:
- ☆19Updated 8 years ago
- RISC-V Virtual Prototype☆186Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- A Tiny Processor Core☆114Updated 6 months ago
- Implementation of TAGE Branch Predictor - currently considered state of the art☆52Updated 11 years ago
- Advanced Architecture Labs with CVA6☆77Updated 2 years ago
- ☆58Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Updated last week
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated this week
- RiVEC Bencmark Suite☆127Updated last year
- Unit tests generator for RVV 1.0☆100Updated 3 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated 3 weeks ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- high-performance RTL simulator☆186Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Pick your favorite language to verify your chip.☆77Updated last week
- ☆90Updated last week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆118Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Scalable Interface for RISC-V ISA Extensions☆23Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated last year