KanPard005 / RISCY_V_TAGE

Related projects ⓘ

Alternatives and complementary repositories for RISCY_V_TAGE

• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆54Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆75Updated this week
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated last month
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆24Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆62Updated last month
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆24Updated last year
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆24Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆42Updated last month
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• arcade-lab / tia-infrastructure
  ☆16Updated 7 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆81Updated 7 months ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆26Updated 4 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆47Updated 4 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆32Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 6 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆30Updated 2 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated last month
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆15Updated 2 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆15Updated 2 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• sequencer / arithmetic
  ☆31Updated last month
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 5 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month