Unified Verification Environment
☆17Jan 17, 2017Updated 9 years ago
Alternatives and similar repositories for uve
Users that are interested in uve are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- CI Docker Images☆19Jan 1, 2021Updated 5 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆40May 9, 2022Updated 3 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 5 months ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Mirror of git://git.zerfleddert.de/usb-driver☆20Aug 9, 2013Updated 12 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- Board repository for the Arty Z7☆14Aug 21, 2017Updated 8 years ago
- E2E tests for the Beats☆18Aug 8, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated 3 months ago
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- https://hackaday.io/project/20039-pocket-thermal-camera☆14Sep 11, 2017Updated 8 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 2 months ago
- This is a demo program for using OpenCV3.0 with Swift and C++.☆13Dec 3, 2014Updated 11 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An ultrasonic water flowmeter based on transit-time technique☆17Jul 21, 2021Updated 4 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- ☆18Jan 3, 2024Updated 2 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆16Nov 9, 2023Updated 2 years ago
- A free, fast and compact ARM Cortex-M0 floating-point library☆16May 26, 2021Updated 4 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- DEPRECATED: Moved to https://github.com/elastic/beats/tree/master/dev-tools/packer☆16Aug 8, 2024Updated last year
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- ☆16Feb 5, 2021Updated 5 years ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆251Apr 20, 2026Updated last week
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 5 months ago
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- An ESP8266 / LUA / php based burglar alert☆11May 1, 2015Updated 11 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago