Unified Verification Environment
☆17Jan 17, 2017Updated 9 years ago
Alternatives and similar repositories for uve
Users that are interested in uve are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 7 years ago
- CI Docker Images☆19Jan 1, 2021Updated 5 years ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆40May 9, 2022Updated 4 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 7 months ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- Board repository for the Arty Z7☆14Aug 21, 2017Updated 8 years ago
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 11 years ago
- E2E tests for the Beats☆19Aug 8, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 5 months ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 4 months ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- An ultrasonic water flowmeter based on transit-time technique☆17Jul 21, 2021Updated 4 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆17Nov 9, 2023Updated 2 years ago
- A free, fast and compact ARM Cortex-M0 floating-point library☆17May 26, 2021Updated 5 years ago
- DEPRECATED: Moved to https://github.com/elastic/beats/tree/master/dev-tools/packer☆16Aug 8, 2024Updated last year
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- ☆16Feb 5, 2021Updated 5 years ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆255Updated this week
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 7 months ago
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- FPGA development in PlatformIO, using the Icestorm opensource toolchain☆21Oct 22, 2016Updated 9 years ago
- Dump contents of Windows EXE and DLL as text.☆27Nov 2, 2023Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆52Jan 13, 2021Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆20Apr 27, 2024Updated 2 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago