uve-project / uve
Unified Verification Environment
☆17Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for uve
- Extensible FPGA control platform☆54Updated last year
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Torc: Tools for Open Reconfigurable Computing☆39Updated 7 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Utilities for MyHDL☆17Updated 11 months ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆27Updated 11 years ago
- Wishbone controlled I2C controllers☆44Updated last week
- ☆22Updated last year
- IP-core package generator for AXI4/Avalon☆21Updated 6 years ago
- Small footprint and configurable JESD204B core☆40Updated last month
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆9Updated 9 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Yosys Plugins☆20Updated 5 years ago
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 8 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- CMod-S6 SoC☆36Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Library of reusable VHDL components☆25Updated 8 months ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 5 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- Verilog Repository for GIT☆30Updated 3 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆20Updated 8 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago