This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target det…
☆44Feb 17, 2019Updated 7 years ago
Alternatives and similar repositories for Motion-Detection-System-Based-On-Background-Reconstruction
Users that are interested in Motion-Detection-System-Based-On-Background-Reconstruction are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 7 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- FPGA实现动态图像识别☆23Jul 31, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆31Jan 23, 2021Updated 5 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 7 years ago
- 集成电路设计大赛ARM杯作品，获得2021年ARM企业杯☆16Sep 26, 2021Updated 4 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆32Jul 21, 2018Updated 7 years ago
- 帧差法运动目标检测，基于ZYNQ7020☆83Jul 9, 2021Updated 4 years ago
- 一种基于FPGA平台的实时视频去雾系统项目代码，其中bit流文件可以直接下载到PYNQ-Z2开发板上，通过usb和hdmi设备输入有雾视频，将去雾后的视频输出到显示屏上。c++源代码部分是我们的去雾IP核的源代码。☆20Nov 24, 2019Updated 6 years ago
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆21Sep 2, 2023Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- This is just for Takk_Zynq_Labs test.☆27Jan 14, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Oct 7, 2019Updated 6 years ago
- A novel architectural design for stitching video streams in real-time on an FPGA.☆137Oct 25, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- A simple, scalable, source-synchronous, all-digital DDR link☆36Mar 17, 2026Updated last week
- Pynq projects and guides☆29Sep 11, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Face recognition, computer vision, deep learning, PYNQ, Movidius NCS☆61Jan 29, 2019Updated 7 years ago
- ☆30Jul 9, 2025Updated 8 months ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆10Jul 28, 2019Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Radix-4 1024 point fft in verilog☆13Apr 29, 2020Updated 5 years ago
- "智能公交系统电子站牌设计"毕业设计单片机和微信小程序代码☆13Jan 11, 2023Updated 3 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Axiom Alpha prototype software (FPGA, Linux, etc.)☆30Dec 9, 2015Updated 10 years ago
- OpenVX Running on a Raspberry Pi☆16Mar 27, 2017Updated 9 years ago
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- ☆17Mar 30, 2023Updated 2 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.☆47Feb 22, 2017Updated 9 years ago
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆12Apr 15, 2023Updated 2 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆904Jul 29, 2024Updated last year
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 7 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago