Alternatives and similar repositories for iron

Users that are interested in iron are comparing it to the libraries listed below

• necst / xlnx-project-template
  Template Repository for Xilinx HLS design flow
  ☆12Updated 3 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆39Updated 6 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆91Updated 8 months ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆18Updated last year
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆27Updated 2 years ago
• ic-lab-duth / FusedGCN4HLS
  Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
  ☆22Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 10 months ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated 10 months ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 7 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• SFU-HiAccel / rodinia-hls
  FPGA version of Rodinia in HLS C/C++
  ☆35Updated 4 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆59Updated 3 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 3 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆18Updated last month
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• maestro-project / gamma-timeloop
  ☆15Updated last year
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated 3 weeks ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago