AlbertoParravicini / segretini-matplottiniLinks
A collection of Matplotlib and Seaborn recipes and utilities collected over years of colorful plot-making
☆22Updated 2 years ago
Alternatives and similar repositories for segretini-matplottini
Users that are interested in segretini-matplottini are comparing it to the libraries listed below
Sorting:
- Template Repository for Xilinx HLS design flow☆12Updated 4 years ago
- ☆14Updated last year
- ☆16Updated last week
- ☆87Updated last year
- Open source RTL simulation acceleration on commodity hardware☆32Updated 2 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆28Updated 2 months ago
- An EDA toolchain for integrated core-memory interval thermal simulations of 2D, 2.5, and 3D multi-/many-core processors☆51Updated 3 months ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆23Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 5 months ago
- ☆15Updated 3 years ago
- ☆14Updated 2 years ago
- A research shell for Alveo V80☆19Updated 3 weeks ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 4 months ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆22Updated 5 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆92Updated 5 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- ☆33Updated 10 months ago
- ☆37Updated 4 months ago
- ☆13Updated last month
- ☆15Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- SoC design & prototyping☆16Updated 5 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆114Updated last week
- The Task Parallel System Composer (TaPaSCo)☆111Updated this week
- CGRA framework with vectorization support.☆39Updated last week
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year