Alternatives and similar repositories for segretini-matplottini

Users that are interested in segretini-matplottini are comparing it to the libraries listed below

• necst / xlnx-project-template
  Template Repository for Xilinx HLS design flow
  ☆12Updated 3 years ago
• Xilinx / SLASH
  A research shell for Alveo V80
  ☆17Updated 2 weeks ago
• necst / iron
  Image Registration on FPGAs
  ☆21Updated 3 years ago
• DSDL-EE / PYNQ-ZU_Tutorial
  ☆13Updated 2 years ago
• ATaylorCEngFIET / Professional-PYNQ
  ☆14Updated last year
• lana555 / dynamatic
  ☆87Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 2 months ago
• emanueledelsozzo / awesome-fpga-programming
  An awesome curated list of languages and tools to program FPGAs
  ☆64Updated 3 years ago
• AGS-L / DynaRapid
  ☆15Updated last week
• ECASLab / cynq
  PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
  ☆26Updated this week
• wincle626 / HLS_Legup
  ☆28Updated 7 years ago
• VeriGOOD-ML / public
  ☆63Updated 4 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆113Updated this week
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆24Updated 3 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• Deepak42074 / Sky130-RTL-Design-And-Synthesis-Using-Verilog
  ☆15Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated last month
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆22Updated 9 months ago
• SFU-HiAccel / rodinia-hls
  FPGA version of Rodinia in HLS C/C++
  ☆39Updated 4 years ago
• MEEPproject / fpga_shell
  MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
  ☆14Updated last year
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆29Updated 5 months ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆39Updated last week
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago