AlbertoParravicini / segretini-matplottiniLinks
A collection of Matplotlib and Seaborn recipes and utilities collected over years of colorful plot-making
☆22Updated 2 years ago
Alternatives and similar repositories for segretini-matplottini
Users that are interested in segretini-matplottini are comparing it to the libraries listed below
Sorting:
- Template Repository for Xilinx HLS design flow☆12Updated 4 years ago
- Image Registration on FPGAs☆21Updated 3 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆27Updated 2 weeks ago
- ☆14Updated 2 years ago
- A research shell for Alveo V80☆21Updated 3 weeks ago
- Chisel Project for Integrating RTL code into SDAccel☆17Updated 7 years ago
- ☆87Updated last year
- ☆15Updated 6 months ago
- ☆17Updated last month
- ☆13Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆60Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 7 months ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Updated 11 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆30Updated 9 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 7 months ago
- Alveo Versal Example Design☆52Updated 3 weeks ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆30Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- Resource Utilization and Latency Estimation for ML on FPGA.☆17Updated 3 months ago
- An awesome curated list of languages and tools to program FPGAs☆72Updated 3 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆12Updated last year