AngeloJacobo / FPGA_RealTime_and_Static_Sobel_Edge_DetectionLinks
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
☆61Updated 3 years ago
Alternatives and similar repositories for FPGA_RealTime_and_Static_Sobel_Edge_Detection
Users that are interested in FPGA_RealTime_and_Static_Sobel_Edge_Detection are comparing it to the libraries listed below
Sorting:
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆63Updated 2 years ago
- Pipeline FFT Implementation in Verilog HDL☆128Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆130Updated 4 years ago
- Lecture about FIR filter on an FPGA☆12Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆154Updated 5 months ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated 2 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆64Updated 3 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆37Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆62Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆36Updated 4 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- AHB3-Lite Interconnect☆90Updated last year
- This is a detailed SystemVerilog course☆114Updated 5 months ago
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- ☆163Updated 2 years ago
- ☆47Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆367Updated last year
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆106Updated 7 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- APB to I2C☆44Updated 11 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆28Updated 6 years ago
- Verilog UART☆178Updated 12 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆46Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆89Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆96Updated 2 years ago