Alternatives and similar repositories for kitty:

Users that are interested in kitty are comparing it to the libraries listed below

• lsils / bill
  C++ header-only reasoning library
  ☆13Updated 7 months ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆35Updated 7 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆24Updated 2 years ago
• msoeken / cirkit
  A circuit toolkit
  ☆97Updated 4 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated 2 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆63Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆27Updated 7 months ago
• lsils / mockturtle
  C++ logic network library
  ☆221Updated 4 months ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆67Updated this week
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆192Updated 10 months ago
• gmeuli / caterpillar
  ☆23Updated 4 years ago
• nbulsi / also
  A logic synthesis tool
  ☆72Updated 2 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆102Updated 3 months ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆20Updated 2 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆30Updated 3 years ago
• amahzoon / genmul
  ☆15Updated 4 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆65Updated this week
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆12Updated 5 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 2 months ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated last week
• cornell-zhang / datuner
  DATuner Repository
  ☆18Updated 6 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated last month
• gipsyh / rIC3
  Hardware Model Checker
  ☆30Updated this week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆23Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆63Updated this week
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆12Updated last year