betrusted-io / betrusted-socView external linksLinks
Betrusted main SoC design
☆156Jul 22, 2025Updated 6 months ago
Alternatives and similar repositories for betrusted-soc
Users that are interested in betrusted-soc are comparing it to the libraries listed below
Sorting:
- IP submodules, formatted for easier CI integration☆31Sep 22, 2025Updated 4 months ago
- Betrusted embedded controller (UP5K)☆49Dec 22, 2023Updated 2 years ago
- betrusted.io main SoC design☆14Jan 30, 2020Updated 6 years ago
- The Xous microkernel☆848Updated this week
- LiteX based FPGA gateware for Thunderscope.☆28Feb 6, 2024Updated 2 years ago
- Support files for participating in a Fomu workshop☆169Mar 17, 2024Updated last year
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- Documentation on the Xous operating system☆42Jan 18, 2026Updated last month
- Bootloader for Fomu☆105Dec 31, 2022Updated 3 years ago
- Template project for LiteX-based SoCs☆21Jan 8, 2026Updated last month
- LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.☆19Dec 11, 2025Updated 2 months ago
- ☆13Nov 14, 2022Updated 3 years ago
- A user manual and technical reference for the Neotron family☆39Oct 19, 2024Updated last year
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆40Aug 16, 2021Updated 4 years ago
- Build your hardware, easily!☆3,722Feb 11, 2026Updated last week
- ☆17Aug 16, 2023Updated 2 years ago
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆17Oct 7, 2025Updated 4 months ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆219May 21, 2022Updated 3 years ago
- USB3 PIPE interface for Xilinx 7-Series☆246Jan 2, 2026Updated last month
- Multi-platform nightly builds of open source FPGA tools☆301Nov 3, 2021Updated 4 years ago
- A Python toolbox for building complex digital hardware☆1,322Jan 5, 2026Updated last month
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated last year
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 4 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆682Jan 8, 2022Updated 4 years ago
- FPGA 101 lessons/labs☆406Jul 14, 2024Updated last year
- FPGA board-level debugging and reverse-engineering tool☆39Mar 24, 2023Updated 2 years ago
- FuseSoC standard core library☆153Dec 8, 2025Updated 2 months ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆57Updated this week
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- an experimental SDR platform☆44Feb 8, 2023Updated 3 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆91Nov 7, 2024Updated last year
- making printf work for you☆15Nov 10, 2025Updated 3 months ago
- ECP5 FPGA DEV BOARD☆10Apr 19, 2021Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,130Sep 22, 2025Updated 4 months ago
- assorted library of utility cores for amaranth HDL☆102Sep 17, 2024Updated last year
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆26Feb 21, 2022Updated 3 years ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,983Updated this week