hadarshavit / revisiting_satzillaLinks
SATZilla SAT feature extraction tool
☆11Updated last year
Alternatives and similar repositories for revisiting_satzilla
Users that are interested in revisiting_satzilla are comparing it to the libraries listed below
Sorting:
- ☆14Updated 7 years ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆21Updated 4 months ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 2 years ago
- Python version of tools to work with AIG formatted files☆12Updated 4 months ago
- A Python/C++ implementation of Quine McCluskey(Tabulation) method.☆12Updated 7 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆36Updated last year
- py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).☆47Updated 9 months ago
- ☆12Updated 2 years ago
- Arithmetic multiplier benchmarks☆11Updated 7 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 5 months ago
- Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)☆25Updated 2 years ago
- ☆15Updated 2 years ago
- PyTorch implementation of NeuroSAT☆28Updated 2 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆12Updated 2 months ago
- ☆11Updated 9 months ago
- A high-efficiency hybrid solving CEC algorithm☆13Updated 2 years ago
- ☆16Updated last year
- A Simple CDCL Solver☆31Updated 2 years ago
- Tools for manipulating CHC and related files☆15Updated 2 years ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Updated 4 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 11 months ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Updated 2 years ago
- An advanced circuit-based sat solver☆29Updated 7 months ago
- ☆18Updated 4 years ago
- ☆15Updated 2 years ago