Alternatives and similar repositories for Security-Engine:

Users that are interested in Security-Engine are comparing it to the libraries listed below

• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆25Updated 3 weeks ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆13Updated last year
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆13Updated 11 months ago
• vsdip / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆14Updated 4 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 9 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆11Updated last month
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆12Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆37Updated 4 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 3 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated this week
• PeterMonsson / sv_waveterm
  ☆9Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated 2 weeks ago
• arhamhashmi01 / rv32i-pipeline-processor
  This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
  ☆10Updated 10 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆14Updated 7 months ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆36Updated 3 years ago
• vsdip / avsddac_3v3_sky130_v1
  ☆12Updated 2 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆19Updated 10 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 8 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆17Updated last year
• merldsu / PY_UVM_Framework
  This repo contain the PY-UVM Framework for different RISC-V Cores
  ☆31Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆21Updated 5 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆18Updated 2 months ago