pulp-platform / RVfplib
Optimized RISC-V FP emulation for 32-bit processors
☆32Updated 3 years ago
Alternatives and similar repositories for RVfplib:
Users that are interested in RVfplib are comparing it to the libraries listed below
- SoftCPU/SoC engine-V☆54Updated last month
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆97Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- Spen's Official OpenOCD Mirror☆49Updated last month
- RISC-V Nox core☆62Updated 3 weeks ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆95Updated last month
- RISC-V Core Local Interrupt Controller (CLINT)☆25Updated last year
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆17Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- RISC-V processor☆29Updated 2 years ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A pipelined RISC-V processor☆55Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- HF-RISC SoC☆32Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆41Updated 4 months ago
- A RISC-V processor☆13Updated 6 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆54Updated this week