FuyuWang / SoterLinks
☆12Updated 11 months ago
Alternatives and similar repositories for Soter
Users that are interested in Soter are comparing it to the libraries listed below
Sorting:
- Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators☆119Updated 3 years ago
- ☆214Updated 2 months ago
- ☆12Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 9 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆106Updated 7 months ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆105Updated last year
- ☆141Updated last week
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆65Updated last year
- OSDI 2023 Welder, deeplearning compiler☆28Updated 2 years ago
- ☆115Updated last year
- ☆42Updated last year
- ☆18Updated last year
- An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation☆54Updated last year
- Research about dataflow architecture☆12Updated 2 years ago
- ☆113Updated 2 years ago
- A Row Decomposition-based Approach for Sparse Matrix Multiplication on GPUs☆27Updated 2 years ago
- ☆47Updated 4 years ago
- EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator☆14Updated 6 months ago
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆20Updated last year
- WaferLLM: Large Language Model Inference at Wafer Scale☆78Updated last month
- A co-design architecture on sparse attention☆54Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆45Updated 3 years ago
- ☆40Updated 2 weeks ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆29Updated 2 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆78Updated 8 months ago
- UPMEM LLM Framework allows profiling PyTorch layers and functions and simulate those layers/functions with a given hardware profile.☆37Updated 4 months ago