mbalestrini / GDS-Cell-Library-Render
☆10Updated 2 years ago
Alternatives and similar repositories for GDS-Cell-Library-Render
Users that are interested in GDS-Cell-Library-Render are comparing it to the libraries listed below
Sorting:
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 4 months ago
- Parasitic Extraction for KLayout☆20Updated last week
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated last year
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Characterizer☆22Updated 8 months ago
- ☆36Updated 2 years ago
- Parasitic capacitance analysis of foundry metal stackups☆12Updated last week
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆26Updated 2 years ago
- SAR ADC on tiny tapeout☆38Updated 3 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated 2 weeks ago
- Hdl21 Schematics☆14Updated last year
- ☆18Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Interchange formats for chip design.☆29Updated last week
- A configurable SRAM generator☆48Updated 4 months ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- Open source process design kit for 28nm open process☆55Updated last year
- ☆12Updated 3 years ago
- BAG framework☆40Updated 9 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆13Updated last year
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- Cross EDA Abstraction and Automation☆38Updated this week
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- skywater 130nm pdk☆28Updated last week
- ☆31Updated 4 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago