mbalestrini / GDS-Cell-Library-RenderLinks
☆10Updated 2 years ago
Alternatives and similar repositories for GDS-Cell-Library-Render
Users that are interested in GDS-Cell-Library-Render are comparing it to the libraries listed below
Sorting:
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated 2 weeks ago
- ☆37Updated 3 years ago
- Characterizer☆28Updated last month
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Online viewer of Xschem schematic files☆26Updated 7 months ago
- Interchange formats for chip design.☆31Updated 2 months ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 3 years ago
- ☆44Updated 5 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 3 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆42Updated 4 months ago
- Hdl21 Schematics☆14Updated last year
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated last month
- A configurable SRAM generator☆53Updated last week
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year
- BAG framework☆41Updated 11 months ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- mantle library☆44Updated 2 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆11Updated last week
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12Updated 4 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- End-to-End Open-Source I2C GPIO Expander☆32Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago