mbalestrini / GDS-Cell-Library-Render
☆10Updated 2 years ago
Alternatives and similar repositories for GDS-Cell-Library-Render:
Users that are interested in GDS-Cell-Library-Render are comparing it to the libraries listed below
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 2 months ago
- Open source process design kit for 28nm open process☆49Updated 10 months ago
- A configurable SRAM generator☆44Updated last month
- ☆36Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆47Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Characterizer☆21Updated 6 months ago
- Parasitic capacitance analysis of foundry metal stackups☆10Updated this week
- Library of open source Process Design Kits (PDKs)☆33Updated last week
- Benchmarks for Yosys development☆23Updated 5 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆12Updated 10 months ago
- Hdl21 Schematics☆14Updated last year
- Extended and external tests for Verilator testing☆16Updated last week
- Cross EDA Abstraction and Automation☆36Updated last week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Digital Circuit rendering engine☆37Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- ☆31Updated last month
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 7 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆39Updated 7 months ago
- A set of rules and recommendations for analog and digital circuit designers.☆27Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 3 months ago
- An automatic clock gating utility☆44Updated 7 months ago