tomverbeure / panologic
PanoLogic Zero Client G1 reverse engineering info
☆69Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for panologic
- Pano Logic G2 Reverse Engineering Project☆137Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Miscellaneous ULX3S examples (advanced)☆74Updated last year
- Software, Firmware and documentation for the myStorm BlackIce-II board☆68Updated 3 years ago
- A simple GPU on a TinyFPGA BX☆80Updated 6 years ago
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆33Updated 5 years ago
- A FPGA core for a simple SDRAM controller.☆115Updated 2 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- List of all links you can try with ULX3S☆93Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- FPGA USB stack written in LiteX☆125Updated 2 years ago
- A wishbone controlled scope for FPGA's☆72Updated 9 months ago
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆78Updated 3 years ago
- An Open Source configuration of the Arty platform☆122Updated 9 months ago
- 妖刀夢渡☆56Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- USB Serial on the TinyFPGA BX☆132Updated 3 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆85Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆33Updated 6 years ago
- Upduino v2 with the ice40 up5k FPGA demos☆78Updated last year
- A CPU on an FPGA that you can play Zork on☆49Updated 7 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆54Updated last year
- IBM PC Compatible SoC for a commercially available FPGA board☆67Updated 8 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- open-source logic analyzer for FPGAs☆96Updated 6 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆36Updated 4 years ago
- Tools and Examples for IcoBoard☆79Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- Using the TinyFPGA BX USB code in user designs☆49Updated 5 years ago