UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
☆10Dec 9, 2023Updated 2 years ago
Alternatives and similar repositories for SPI_Protocol
Users that are interested in SPI_Protocol are comparing it to the libraries listed below
Sorting:
- ☆10Nov 2, 2023Updated 2 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆40Jun 24, 2020Updated 5 years ago
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 5 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆49Mar 3, 2024Updated 2 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated last year
- Verification of an Asynchronous FIFO using UVM & SVA☆11Jun 26, 2025Updated 8 months ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 13 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- SystemVerilog examples for a digital design course☆13Mar 30, 2021Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆52Jul 4, 2020Updated 5 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 7 months ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 10 years ago
- SystemVerilog extension for Visual Studio Code☆13Dec 18, 2018Updated 7 years ago
- ☆10Nov 30, 2022Updated 3 years ago
- This repository is a collection of designs invloving FPGAs and AI technologies.☆14Jan 11, 2023Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago
- ☆17Sep 5, 2025Updated 5 months ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆61May 27, 2020Updated 5 years ago
- ☆15Dec 1, 2022Updated 3 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Feb 25, 2023Updated 3 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- Extended and external tests for Verilator testing☆17Updated this week
- ☆15Jun 27, 2024Updated last year
- ☆17Jan 13, 2024Updated 2 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆19Mar 7, 2024Updated last year
- The implemention & test code for xilinx fft ip core(v 9.0), standard AIX4, for future reference☆16Jul 14, 2019Updated 6 years ago
- SystemVerilog stuff and stuff.☆12Jun 2, 2016Updated 9 years ago
- General Purpose I/O agent written in UVM☆18Jun 29, 2017Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆12Oct 8, 2017Updated 8 years ago
- ☆18Oct 5, 2020Updated 5 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago