Alternatives and similar repositories for vhdl-tutorial

Users that are interested in vhdl-tutorial are comparing it to the libraries listed below

• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆149Updated 3 weeks ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆132Updated 3 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆129Updated last week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆201Updated 3 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 5 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆74Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆62Updated 2 years ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆141Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆53Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆105Updated last week
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆249Updated last week
• HDLForBeginners / Examples
  ☆93Updated last year
• bluecmd / learn-sky130
  Learning to do things with the Skywater 130nm process
  ☆81Updated 4 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆177Updated last month
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆106Updated 4 years ago
• Marco-Winzker / NN_RGB_FPGA
  FPGA Design of a Neural Network for Color Detection
  ☆76Updated 4 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆330Updated 3 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆110Updated 2 weeks ago
• mattvenn / awesome-opensource-asic-resources
  ☆323Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆147Updated 11 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆389Updated 5 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆128Updated 6 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆118Updated 4 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆138Updated 5 years ago