Alternatives and similar repositories for onlinehd

Users that are interested in onlinehd are comparing it to the libraries listed below

• mean9park / BitFusion-verilog
  bitfusion verilog implementation
  ☆8Updated 3 years ago
• BaoBao-zhu / RV-SCNN
  A Custom RISC-V Instruction Extension for SNN and CNN Computation
  ☆15Updated 9 months ago
• oshears / SNN-FPGA-Implementation
  ☆19Updated 4 years ago
• Minz9 / SNN-on-FPGA
  SNN on FPGA
  ☆10Updated 3 years ago
• RuokaiYin / LoAS
  LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
  ☆11Updated 2 months ago
• booniebears / CoMN
  ☆15Updated last year
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 11 months ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• m-spr / RCEHDC
  An automated HDC platform
  ☆9Updated 2 months ago
• bonanyan / attentionlego
  Attentionlego
  ☆12Updated last year
• DanielGerlinghoff / radix-encoding
  Framework for radix encoded SNN on FPGA
  ☆13Updated 3 years ago
• Intelligent-Microsystems-Lab / SNNQuantPrune
  Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"
  ☆11Updated 2 years ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆24Updated this week
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆11Updated last year
• Deepak42074 / SRAM_IMC_MPW8
  The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…
  ☆11Updated 2 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆12Updated 3 years ago
• Stanzzz77 / SNN-NEST_Simulator_2.14.0-xilinx-ZCU102
  A nest brain simulator based on FPGA(LIF NEURON)
  ☆14Updated 3 years ago
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• eardbi / hd-vhdl-library
  ☆10Updated 6 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• Intelligent-Microsystems-Lab / QuantizedLSTM
  Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).
  ☆15Updated 4 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆34Updated 5 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• fabio-montagna / PULP-HD
  ☆11Updated 7 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆48Updated 4 years ago
• I-Doctor / RTL_library_of_basic_hardware_units
  Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …
  ☆11Updated last year
• adamgallas / FireFly-v2
  [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…
  ☆19Updated last year
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆13Updated 3 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆26Updated last year