ESCristiano / BUStedLinks
BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
☆11Updated last year
Alternatives and similar repositories for BUSted
Users that are interested in BUSted are comparing it to the libraries listed below
Sorting:
- CROSSCON-Hypervisor, a Lightweight Hypervisor☆19Updated last month
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆71Updated 6 months ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- ☆23Updated 5 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆65Updated 5 years ago
- Group administration repository for Tech: IOPMP Task Group☆13Updated 9 months ago
- RISC-V IOMMU Demo (Linux & Bao)☆23Updated last year
- RISC-V Security HC admin repo☆18Updated 8 months ago
- Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.☆11Updated 6 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- RISC-V Security Model☆32Updated this week
- This is the main repository of the ALFA framework project! Jump here to start developping with ALFA.☆16Updated 3 months ago
- ☆23Updated 6 months ago
- ☆70Updated 4 months ago
- ☆18Updated 3 years ago
- Security Test Benchmark for Computer Architectures☆21Updated last week
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆60Updated this week
- ☆22Updated 2 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆135Updated last year
- ☆115Updated 2 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆57Updated last month
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 3 years ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- ☆25Updated 2 years ago
- ☆11Updated 5 months ago
- HW Design Collateral for Caliptra RoT IP☆112Updated this week
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆55Updated 6 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- IOPMP IP☆19Updated 2 months ago