ThalesGroup / RISC-V-IoT-Contest

Related projects ⓘ

Alternatives and complementary repositories for RISC-V-IoT-Contest

• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆30Updated 10 months ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• daniellustig / pipecheck
  ☆18Updated 9 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆20Updated 3 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆17Updated 4 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated last year
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆55Updated last month
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• sifive / last-week-in-risc-v
  Weekly RISC-V Newsletter
  ☆28Updated 5 years ago
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆25Updated 5 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• riscv / riscv-test-env
  ☆40Updated 5 months ago
• daniellustig / coatcheck
  COATCheck
  ☆12Updated 6 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• RISCV-on-Microsemi-FPGA / CPUs
  CPUs
  ☆13Updated 3 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 7 months ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆41Updated 4 months ago
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆52Updated last week
• Minres / DBT-RISE-RISCV
  An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
  ☆34Updated last month
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆18Updated this week
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated last year
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆56Updated this week
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago