lizhirui / fpga-high-speed-stream-protocol
This stream transmission protocol is used for data transmission between some fpgas.
☆9Updated 3 years ago
Alternatives and similar repositories for fpga-high-speed-stream-protocol:
Users that are interested in fpga-high-speed-stream-protocol are comparing it to the libraries listed below
- ☆17Updated 2 years ago
- Run Rocket Chip on VCU128☆29Updated 3 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- nscscc2018☆26Updated 6 years ago
- ☆12Updated 2 years ago
- The 'missing header' for Chisel☆18Updated 3 weeks ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- ☆32Updated 3 weeks ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆26Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆15Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆34Updated last year
- Rewrite XuanTieC910 with chisel3☆11Updated 2 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- riscv32i-cpu☆19Updated 4 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Implements kernels with RISC-V Vector☆22Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Lower chisel memories to SRAM macros☆12Updated 11 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 3 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Updated 4 years ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆9Updated 5 years ago
- A tool to convert binary files to COE files 💫☆14Updated last month
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Updated 4 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- Wrappers for open source FPU hardware implementations.☆30Updated 11 months ago
- ☆31Updated last week