Alternatives and similar repositories for nand2tetris-iverilog

Users that are interested in nand2tetris-iverilog are comparing it to the libraries listed below

• leros-dev / leros
  A Tiny Processor Core
  ☆112Updated 2 months ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 4 years ago
• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆148Updated 10 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆54Updated 2 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆87Updated last year
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆90Updated 7 years ago
• lightcode / 8bit-computer
  A simple 8-bit computer build in Verilog.
  ☆68Updated 4 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated 3 weeks ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆155Updated last month
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆169Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆94Updated 5 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 4 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆111Updated last month
• risclite / R8051
  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
  ☆190Updated 6 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆354Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 6 months ago
• MIPSfpga / schoolMIPS
  CPU microarchitecture, step by step
  ☆202Updated 4 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆50Updated 2 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆386Updated 3 months ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆149Updated last year
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆157Updated 3 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 4 years ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆125Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆182Updated 2 weeks ago