ejrh / cpuLinks
A very primitive but hopefully self-educational CPU in Verilog
☆150Updated 10 years ago
Alternatives and similar repositories for cpu
Users that are interested in cpu are comparing it to the libraries listed below
Sorting:
- A simple RISC-V processor for use in FPGA designs.☆282Updated last year
- A simple RISC V core for teaching☆196Updated 3 years ago
- Verilog implementation of a RISC-V core☆129Updated 7 years ago
- An open source CPU design and verification platform for academia☆112Updated 2 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- RISC-V CPU Core☆393Updated 4 months ago
- CPU microarchitecture, step by step☆203Updated 5 years ago
- OpenRISC 1200 implementation☆173Updated 10 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- A simple, basic, formally verified UART controller☆314Updated last year
- Implemetation of pipelined ARM7TDMI processor in Verilog☆90Updated 7 years ago
- Ariane is a 6-stage RISC-V CPU☆151Updated 5 years ago
- A Tiny Processor Core☆114Updated 4 months ago
- Basic RISC-V CPU implementation in VHDL.☆171Updated 5 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆563Updated 2 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- A Video display simulator☆174Updated 6 months ago
- Basic RISC-V Test SoC☆159Updated 6 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆156Updated 7 years ago
- Various caches written in Verilog-HDL☆127Updated 10 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆675Updated 4 months ago
- RISC-V soft-core microcontroller for FPGA implementation☆186Updated last month
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆143Updated 3 years ago
- Verilog SDRAM memory controller☆350Updated 8 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆150Updated 9 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆364Updated 8 years ago
- A simple implementation of a UART modem in Verilog.☆164Updated 4 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated last week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago