Alternatives and similar repositories for cpu

Users that are interested in cpu are comparing it to the libraries listed below

• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆102Updated 4 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆274Updated 9 months ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆124Updated 10 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆327Updated 11 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆189Updated 3 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆137Updated 5 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆116Updated 4 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆89Updated 7 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆134Updated 3 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆168Updated 2 weeks ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆147Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆118Updated 6 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 8 months ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆169Updated 9 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆132Updated 2 years ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆173Updated last month
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆324Updated 3 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆360Updated 7 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆128Updated 6 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago