A very primitive but hopefully self-educational CPU in Verilog
☆154Jan 21, 2015Updated 11 years ago
Alternatives and similar repositories for cpu
Users that are interested in cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MIPS CPU implemented in Verilog☆658Oct 3, 2017Updated 8 years ago
- A simulator for a simple RISC CPU in C☆49Mar 6, 2022Updated 4 years ago
- A simple 8-bit computer build in Verilog.☆94Jun 2, 2025Updated last year
- Verification Excellence Knowledge Sharing☆23Jul 14, 2014Updated 12 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆14May 11, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- Tutorial on building your own CPU, in Verilog☆38Apr 25, 2022Updated 4 years ago
- The Easy 8-bit Processor☆186Jun 9, 2014Updated 12 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆128Feb 19, 2016Updated 10 years ago
- Verilog implementation of Ben Eater's 8-bit breadboard computer☆19Sep 12, 2021Updated 5 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,610Sep 4, 2026Updated 2 weeks ago
- Verilog实现的简单五级流水线CPU，开发平台：Nexys3☆40Jul 9, 2015Updated 11 years ago
- Design of a 16-Bit CPU using Verilog☆47Jun 11, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A small, light weight, RISC CPU soft core☆1,586Sep 16, 2026Updated last week
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆82Mar 29, 2023Updated 3 years ago
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 10 years ago
- A Verilog HDL model of the MOS 6502 CPU☆387Apr 8, 2023Updated 3 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 4 years ago
- Example SystemVerilog UVM Environment☆11Jun 23, 2015Updated 11 years ago
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- ☆43Apr 28, 2019Updated 7 years ago
- A self hosting Extended brainfuck to pure brainfuck compiler☆11May 6, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago
- RISC-V CPU Core (RV32IM)☆1,793Sep 18, 2021Updated 5 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆124Oct 2, 2019Updated 6 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆169Jan 20, 2019Updated 7 years ago
- HC-12 library for Arduino☆12Jan 9, 2018Updated 8 years ago
- Verilog implementation of a simple riscv cpu☆19Oct 28, 2021Updated 4 years ago
- ☆41Mar 14, 2025Updated last year
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆20Jul 23, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SPIFFS Bitstreamloader for the Spartan Edge Accelerator Board☆12May 22, 2020Updated 6 years ago
- Verilog UART☆583Feb 27, 2025Updated last year
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- Implementation of a cache memory in verilog☆14Dec 5, 2017Updated 8 years ago
- my UVM training projects☆39Mar 14, 2019Updated 7 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Apr 6, 2019Updated 7 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆630Mar 15, 2018Updated 8 years ago