A very primitive but hopefully self-educational CPU in Verilog
☆154Jan 21, 2015Updated 11 years ago
Alternatives and similar repositories for cpu
Users that are interested in cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MIPS CPU implemented in Verilog☆651Oct 3, 2017Updated 8 years ago
- A simulator for a simple RISC CPU in C☆49Mar 6, 2022Updated 4 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆14May 11, 2026Updated 2 weeks ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Verification Excellence Knowledge Sharing☆24Jul 14, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The Easy 8-bit Processor☆187Jun 9, 2014Updated 11 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- Tutorial on building your own CPU, in Verilog☆35Apr 25, 2022Updated 4 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆127Feb 19, 2016Updated 10 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,553May 12, 2026Updated last week
- Verilog实现的简单五级流水线CPU，开发平台：Nexys3☆40Jul 9, 2015Updated 10 years ago
- Design of a 16-Bit CPU using Verilog☆50Jun 11, 2019Updated 6 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A small, light weight, RISC CPU soft core☆1,544Dec 8, 2025Updated 5 months ago
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆79Mar 29, 2023Updated 3 years ago
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 10 years ago
- Verilog implementation of Ben Eater's 8-bit breadboard computer☆19Sep 12, 2021Updated 4 years ago
- A Verilog HDL model of the MOS 6502 CPU☆377Apr 8, 2023Updated 3 years ago
- FORTH implementation for 65C02☆13Jul 23, 2021Updated 4 years ago
- A self hosting Extended brainfuck to pure brainfuck compiler☆11May 6, 2018Updated 8 years ago
- ☆42Apr 28, 2019Updated 7 years ago
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆121Oct 2, 2019Updated 6 years ago
- RISC-V CPU Core (RV32IM)☆1,719Sep 18, 2021Updated 4 years ago
- An open source CPU design and verification platform for academia☆122Aug 22, 2025Updated 9 months ago
- Verilog implementation of a simple riscv cpu☆19Oct 28, 2021Updated 4 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆20Jul 23, 2022Updated 3 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆162Jan 20, 2019Updated 7 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆60Nov 30, 2022Updated 3 years ago
- Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)☆55Sep 18, 2016Updated 9 years ago
- Verilog UART☆562Feb 27, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Menu bar app to quickly hide or display your desktop files☆12Jan 2, 2023Updated 3 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Apr 6, 2019Updated 7 years ago
- my UVM training projects☆38Mar 14, 2019Updated 7 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆619Mar 15, 2018Updated 8 years ago
- SERV - The SErial RISC-V CPU☆1,801Feb 19, 2026Updated 3 months ago