ejrh / cpu
A very primitive but hopefully self-educational CPU in Verilog
☆137Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for cpu
- A simple RISC-V processor for use in FPGA designs.☆263Updated 3 months ago
- RISC-V CPU Core☆288Updated 5 months ago
- Verilog implementation of a RISC-V core☆102Updated 6 years ago
- A simple RISC V core for teaching☆173Updated 2 years ago
- A simple, basic, formally verified UART controller☆282Updated 9 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆148Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆497Updated last month
- OpenRISC 1200 implementation☆161Updated 9 years ago
- Various caches written in Verilog-HDL☆113Updated 9 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated this week
- RISC-V 32-bit microcontroller developed in Verilog☆158Updated last month
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆357Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆259Updated 4 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆116Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆291Updated 2 months ago
- Verilog SDRAM memory controller☆310Updated 7 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆310Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆217Updated this week
- Common SystemVerilog components☆518Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆271Updated this week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- Code used in☆174Updated 7 years ago
- Instruction Set Generator initially contributed by Futurewei☆266Updated last year
- Verilog UART☆121Updated 11 years ago
- A Tiny Processor Core☆103Updated this week
- An Open-Source Design and Verification Environment for RISC-V☆76Updated 3 years ago
- IEEE 754 floating point unit in Verilog☆128Updated 8 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆225Updated last week