edgarigl / qemu-etrace
Qemu Etrace
☆12Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for qemu-etrace
- A python parser for decoding arm aarch32 and aarch64 system registers☆15Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆24Updated last month
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆20Updated last year
- Coresight Access Library☆112Updated last week
- A RISC-V bare metal example☆43Updated 2 years ago
- Tools for analyzing and browsing Tarmac instruction traces.☆69Updated 3 months ago
- A library for PCIe Transaction Layer☆52Updated 2 years ago
- RISC-V IOMMU Demo (Linux & Bao)☆15Updated 11 months ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆26Updated 3 years ago
- LTZVisor: a Lightweight TrustZone-assisted Hypervisor☆79Updated 6 years ago
- Header-only C library for reading/writing 64-bit Arm registers, automatically generated by parsing the AArch64 System Register XML.☆29Updated 3 years ago
- ☆13Updated 6 months ago
- Side-channel analysis setup for OpenTitan☆28Updated 2 months ago
- Device trees used by QEMU to describe the hardware☆44Updated this week
- Chisel NVMe controller☆13Updated last year
- RISC-V Scratchpad☆59Updated 2 years ago
- PCIe Device Emulation in QEMU☆50Updated last year
- ☆14Updated 10 months ago
- ☆21Updated last month
- C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data e…☆14Updated 2 weeks ago
- embedded-iot_profile☆98Updated 4 years ago
- HW Design Collateral for Caliptra RoT IP☆75Updated this week
- A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux☆25Updated 3 years ago
- TLMu - Transaction Level eMulator☆33Updated 9 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆42Updated last month
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- MultiZone® Security TEE for Arm® Cortex®-M is the quick and safe way to add security and separation to any Cortex-M based device. MultiZo…☆14Updated last year
- ZedBoard Bare Metal examples☆23Updated 3 years ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆42Updated this week
- ARM PTM decoder, and ARM ETM v4 decoder. ptm2human is a decoder for trace data outputted by Program Trace Macrocell (PTM) and Embedded Tr…☆50Updated 2 years ago