IntelLabs / parsacLinks
This is the implementation of the Parallel Simulated Annealing with Constraints (PARSAC) algorithm
☆12Updated 2 weeks ago
Alternatives and similar repositories for parsac
Users that are interested in parsac are comparing it to the libraries listed below
Sorting:
- DATC RDF☆50Updated 4 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆50Updated 5 months ago
- Awesome machine learning for logic synthesis☆28Updated 2 years ago
- ☆25Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- ☆31Updated 3 years ago
- Artificial Netlist Generator☆39Updated last year
- Analog Placement Quality Prediction☆21Updated 2 years ago
- ☆29Updated last year
- DATC Robust Design Flow.☆37Updated 5 years ago
- GPU-based logic synthesis tool☆81Updated this week
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 10 months ago
- SMT-based-STDCELL-Layout-Generator☆18Updated 3 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- ☆72Updated 2 weeks ago
- A LEF/DEF Utility.☆31Updated 5 years ago
- VLSI EDA Global Router☆73Updated 7 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆52Updated 11 months ago
- ☆52Updated 3 weeks ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 10 months ago
- ☆15Updated 7 years ago
- GNN-RE datasets for circuit recognition☆47Updated 2 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆55Updated 3 years ago
- ☆48Updated 3 weeks ago
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆41Updated 2 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆14Updated 2 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 9 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month