Alternatives and similar repositories for parsac:

Users that are interested in parsac are comparing it to the libraries listed below

• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 5 years ago
• IntelLabs / FloorSet
  ☆70Updated 3 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆71Updated 7 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆37Updated last year
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 6 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 8 months ago
• ABKGroup / TritonRoute-WXL
  ☆29Updated 4 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆30Updated 3 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆42Updated 2 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆84Updated 4 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆17Updated 3 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆36Updated 5 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 3 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆20Updated 2 years ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• haiguanl / GlobalRoutingProblemGenerator
  Benchmark Generator for Global Routing
  ☆12Updated 5 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆9Updated 8 years ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆51Updated 4 months ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆51Updated 8 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• CMACH508 / DeepTH
  ☆14Updated 10 months ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• MIRALab-USTC / ChiPBench
  ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms
  ☆28Updated last week
• baloneymath / AncstrGNN
  ☆15Updated 3 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆124Updated 8 months ago