Alternatives and similar repositories for verilog-fpga

Users that are interested in verilog-fpga are comparing it to the libraries listed below

• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 4 months ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆55Updated 4 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆171Updated last week
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆106Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated this week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆63Updated 2 years ago
• HDLForBeginners / Examples
  ☆94Updated last year
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆63Updated 3 weeks ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆23Updated 6 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated 3 weeks ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆96Updated last year
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆66Updated last week
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆59Updated 7 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated last month
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆52Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• TimRudy / uart-verilog
  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
  ☆33Updated 2 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 2 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆92Updated this week
• suoto / fpga_cores
  ☆32Updated 2 years ago