leonow32 / verilog-fpgaLinks
Many peripherals in Verilog ready to use
☆38Updated 8 months ago
Alternatives and similar repositories for verilog-fpga
Users that are interested in verilog-fpga are comparing it to the libraries listed below
Sorting:
- ☆99Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Control and Status Register map generator for HDL projects☆125Updated 3 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- Verilog digital signal processing components☆151Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆67Updated 2 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆177Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- I2C Master Verilog module☆35Updated 2 months ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆44Updated 4 years ago
- A series of CORDIC related projects☆110Updated 9 months ago
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Single Port RAM, Dual Port RAM, FIFO☆26Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- Arduino compatible Risc-V Based SOC☆155Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- A simple implementation of a UART modem in Verilog.☆153Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆59Updated last month
- Verilog UART☆178Updated 12 years ago