leonow32 / verilog-fpga
Many peripherals in Verilog ready to use
☆24Updated this week
Related projects: ⓘ
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆28Updated this week
- A simple DDR3 memory controller☆49Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆84Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆58Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆57Updated 4 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated last month
- ☆32Updated last year
- ☆56Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆55Updated last year
- Open FPGA Modules☆22Updated last week
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆26Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆12Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆40Updated 9 months ago
- UART -> AXI Bridge☆52Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆40Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆34Updated 3 years ago
- Extensible FPGA control platform☆52Updated last year
- ☆40Updated 6 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆72Updated last year
- Open source ISS and logic RISC-V 32 bit project☆32Updated 2 months ago
- Slides and lab instructions for the mastering MicroBlaze session☆31Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆59Updated 2 weeks ago
- Repository gathering basic modules for CDC purpose☆49Updated 4 years ago
- Basic USB-CDC device core (Verilog)☆70Updated 3 years ago
- USB Full Speed PHY☆38Updated 4 years ago
- ☆43Updated 2 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆49Updated 2 years ago
- 10G Low Latency Ethernet☆36Updated last year