Xyce / Xyce_RegressionLinks
The test suite for the Xyce Parallel Electronic Simulator
☆4Updated this week
Alternatives and similar repositories for Xyce_Regression
Users that are interested in Xyce_Regression are comparing it to the libraries listed below
Sorting:
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 5 months ago
- Interchange formats for chip design.☆31Updated 3 weeks ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- ☆44Updated 5 years ago
- ☆20Updated 3 years ago
- BAG framework☆40Updated 10 months ago
- Parasitic Extraction for KLayout☆20Updated this week
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆36Updated 2 years ago
- ☆22Updated 4 years ago
- ☆33Updated 5 years ago
- Open Analog Design Environment☆24Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 5 years ago
- Qucs-Help documentation☆11Updated 6 years ago
- ☆41Updated 2 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆50Updated last year
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆26Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Automatic generation of real number models from analog circuits☆40Updated last year
- skywater 130nm pdk☆28Updated 2 weeks ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A configurable SRAM generator☆50Updated last week
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Cross EDA Abstraction and Automation☆38Updated last week