Alternatives and similar repositories for Xyce_Regression

Users that are interested in Xyce_Regression are comparing it to the libraries listed below

• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆29Updated this week
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated 4 months ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆40Updated last week
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆55Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆23Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆28Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• martinjankoehler / klayout-pex
  Parasitic Extraction for KLayout
  ☆20Updated this week
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆39Updated last year
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆48Updated 4 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago