schoeberl / cae-labLinks
Lab Material for CAE
☆41Updated 11 months ago
Alternatives and similar repositories for cae-lab
Users that are interested in cae-lab are comparing it to the libraries listed below
Sorting:
- A teaching-focused RISC-V CPU design used at UC Davis☆150Updated 2 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆161Updated 5 years ago
- RISC-V Torture Test☆197Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- A Tiny Processor Core☆110Updated last month
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- ☆81Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆156Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆73Updated 2 months ago
- RISC-V Virtual Prototype☆176Updated 8 months ago
- Documentation for RISC-V Spike☆102Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Bluespec BSV HLHDL tutorial☆108Updated 9 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- Comment on the rocket-chip source code☆180Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- ☆90Updated last week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆105Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Chisel examples and code snippets☆257Updated 3 years ago
- A dynamic verification library for Chisel.☆155Updated 9 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆82Updated last month