Alternatives and similar repositories for venus:

Users that are interested in venus are comparing it to the libraries listed below

• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆191Updated 2 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆199Updated 4 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆145Updated last year
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆173Updated 9 months ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆45Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆241Updated 2 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆105Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆163Updated 5 months ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆109Updated 2 months ago
• riscv-software-src / homebrew-riscv
  homebrew (macOS) packages for RISC-V toolchain
  ☆321Updated 2 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆128Updated this week
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 2 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆176Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆180Updated 2 months ago
• USTC-System-Courses / CECS-Lab
  ☆31Updated last year
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆555Updated 5 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆36Updated 6 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 6 months ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆471Updated 2 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆229Updated 4 months ago
• skyzh / mips-simulator
  💻 A 5-stage pipeline MIPS CPU design in Haskell.
  ☆36Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆43Updated 5 years ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 3 years ago
• OpenXiangShan / NEMU
  ☆251Updated this week
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆250Updated 7 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆168Updated 3 weeks ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆173Updated 2 weeks ago