gvsrmk / Design-and-Verification-of-DDR3-SDRAM-memory-controllerView on GitHub
Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various operations. Performed randomized, Constrained, and directed test cases to validate our DUT.
☆11Mar 4, 2020Updated 6 years ago

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