jlpteaching / ECS154B
Materials for ECS 154B at UC Davis
☆36Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for ECS154B
- A teaching-focused RISC-V CPU design used at UC Davis☆143Updated last year
- A Simple As Possible RISCV-32I core with debug module.☆43Updated 4 years ago
- A Hardware Pipeline Description Language☆41Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 4 months ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆76Updated this week
- Extremely Simple Microbenchmarks☆30Updated 6 years ago
- The OpenPiton Platform☆26Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Python wrapper for verilator model☆78Updated 9 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆97Updated 5 years ago
- Ariane is a 6-stage RISC-V CPU☆124Updated 4 years ago
- RISC-V instruction set simulator built for education☆188Updated 2 years ago
- RiVEC Bencmark Suite☆106Updated 3 weeks ago
- An open source CPU design and verification platform for academia☆89Updated 4 years ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆95Updated 7 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- An open source high level synthesis (HLS) tool built on top of LLVM☆118Updated 5 months ago
- ☆33Updated 2 months ago
- (System)Verilog to Chisel translator☆106Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆49Updated 4 years ago
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆60Updated last month
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- ☆36Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- ☆87Updated 8 months ago
- ☆10Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆79Updated 7 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated last year