Alternatives and similar repositories for ECS154B:

Users that are interested in ECS154B are comparing it to the libraries listed below

• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆107Updated last month
• bring-your-own-core / byoc
  The OpenPiton Platform
  ☆28Updated last year
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 5 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆91Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆99Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆102Updated 10 months ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆32Updated last year
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• lana555 / dynamatic
  ☆86Updated 11 months ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 2 months ago
• KireinaHoro / rocket-zynqmp
  ☆13Updated 4 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆90Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• intel / fpga-training
  ☆33Updated 5 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆86Updated 10 months ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆29Updated last week
• darchr / gem5
  Fork of main gem5 repo: https://gem5.googlesource.com/public/gem5/
  ☆21Updated 2 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• mariobadr / synfull-isca
  Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour
  ☆13Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated 7 months ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆145Updated 2 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆119Updated 8 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆50Updated 3 years ago