Alternatives and similar repositories for SPECCPU2017Harmony

Users that are interested in SPECCPU2017Harmony are comparing it to the libraries listed below

• ZenithalHourlyRate / naming
  ☆11Updated last year
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Updated 3 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Updated 2 years ago
• taoky / ayano
  Follow nginx log, and find out bad guys!
  ☆23Updated this week
• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆14Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• thu-cs-lab / jieplag
  Plagiarism detection tool in Rust (inspired by Stanford Moss)
  ☆53Updated 2 months ago
• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆62Updated 3 months ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago
• jiegec / kb
  My knowledge base
  ☆72Updated last week
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 7 months ago
• plctlab / riscv-cluster
  Towards a million-node RISC-V cluster.
  ☆14Updated 8 months ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated last year
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• ZenithalHourlyRate / learn-git-the-not-so-super-hard-way
  ☆17Updated 3 years ago
• CircuitCoder / cidr-calc
  CIDR union / subtraction
  ☆14Updated 2 weeks ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 6 years ago
• KireinaHoro / khtcp
  PKU CompNet'19 Lab 2 - Homebrew TCP
  ☆12Updated 5 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 6 years ago
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆30Updated 5 years ago
• Cytosine2020 / crust
  A Rust style C++ library.
  ☆19Updated 3 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆12Updated 5 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆15Updated 2 years ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• AOSC-Dev / chromium-loongarch64
  Maintain patches for running chromium on loongarch64
  ☆14Updated last week
• ziyao233 / barv
  RISC-V VM in Bash
  ☆29Updated 7 months ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• taoky / tsumugu
  🧵 A HTTP(S) mirroring tool written in Rust, proposed for ustcmirror
  ☆19Updated last week