Alternatives and similar repositories for simulator

Users that are interested in simulator are comparing it to the libraries listed below

• OSCPU / openperf
  ☆11Updated 3 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆26Updated this week
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated 2 weeks ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 3 months ago
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 8 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 6 months ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• puckbee / moli
  ☆11Updated this week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 8 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated this week
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆10Updated last month
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 5 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆19Updated 6 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆36Updated 11 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 2 months ago
• Siudya / Nanhu
  Open-source high-performance RISC-V processor
  ☆29Updated 2 weeks ago
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆20Updated last month
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 4 months ago
• MrAMS / Nagi
  基于difftest改进的CPU敏捷开发框架（龙芯杯2024）
  ☆16Updated 8 months ago
• NJU-ProjectN / riscv-tests-am
  ☆14Updated last year
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated last year
• OSCPU / chisel-playground
  ☆67Updated 3 months ago