OSCPU / openperfLinks
☆11Updated 9 months ago
Alternatives and similar repositories for openperf
Users that are interested in openperf are comparing it to the libraries listed below
Sorting:
- This is an IDE for YSYX_NPC debuging☆12Updated 11 months ago
- 本项目已被合并至官方Chiplab中☆12Updated 10 months ago
- Xiangshan deterministic workloads generator☆22Updated 6 months ago
- ☆62Updated last month
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 10 months ago
- 给NEMU移植Linux Kernel!☆21Updated 5 months ago
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆11Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 7 months ago
- ☆29Updated 9 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 8 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Build mini linux for your own RISC-V emulator!☆24Updated last year
- Basic chisel difftest environment for RTL design (WIP☆19Updated 8 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆21Updated 2 months ago
- A docker image for One Student One Chip's debug exam☆11Updated 2 years ago
- The official website of One Student One Chip project.☆11Updated 2 weeks ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- ☆22Updated 2 years ago
- Documentation for XiangShan Design☆35Updated 3 weeks ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Updated 11 months ago
- ☆31Updated 3 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year
- A fork of Xiangshan for AI☆33Updated 3 weeks ago
- ☆11Updated last year
- ☆33Updated 3 months ago
- ☆74Updated last year
- gem5 FS模式实验手册☆44Updated 2 years ago