Alternatives and similar repositories for openperf:

Users that are interested in openperf are comparing it to the libraries listed below

• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆11Updated 3 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆17Updated 3 weeks ago
• jaypiper / simulator
  ☆19Updated this week
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆13Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated 11 months ago
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆10Updated 2 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated last month
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆15Updated 5 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆20Updated this week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆19Updated 6 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆15Updated this week
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆14Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 2 weeks ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆12Updated 4 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 10 months ago
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆10Updated last month
• MaZirui2001 / Zircon
  ☆23Updated 2 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆23Updated last year
• Jpz-sdju / trinity
  ☆19Updated last week
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆14Updated 6 months ago
• lizhirui / DreamCoreV2
  ☆22Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 4 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆18Updated this week
• OSCPU / chisel-playground
  ☆63Updated last month
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆41Updated 2 weeks ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆34Updated last year
• pku-liang / hestia
  ☆12Updated 2 months ago