Alternatives and similar repositories for 2014_ucsc_fpga:

Users that are interested in 2014_ucsc_fpga are comparing it to the libraries listed below

• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆11Updated 10 months ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆13Updated 10 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆101Updated 11 months ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆32Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆84Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• dineshannayya / usb1_host
  USB1.1 Host Controller + PHY
  ☆13Updated 3 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆59Updated 3 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• freecores / i2c
  I2C controller core
  ☆39Updated 2 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆52Updated 9 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆68Updated 6 years ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆21Updated 5 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆123Updated 2 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆51Updated 4 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• freecores / simple_spi
  SPI core
  ☆12Updated 10 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆62Updated 2 weeks ago
• freecores / uart16550
  UART 16550 core
  ☆34Updated 10 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆36Updated last year
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆70Updated 2 years ago
• makararasi / UVM_AXI4-Stream
  ☆13Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆40Updated 6 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 4 months ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago