Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
☆89Mar 21, 2026Updated 7 months ago
Alternatives and similar repositories for MicroBlaze-DDR3-tutorial
Users that are interested in MicroBlaze-DDR3-tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.☆44Apr 4, 2026Updated 6 months ago
- A fairly low-cost 4-layer AMD/Xilinx Artix-7 FPGA development board designed in KiCad, with bidirectional and unidirectional high-speed s…☆13Aug 24, 2024Updated 2 years ago
- ☆13Oct 18, 2026Updated 2 weeks ago
- FPGA-based real-time audio spectrum analyzer.☆11Feb 18, 2024Updated 2 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Rust support for the open-source NEORV32 RISC-V microcontroller.☆14Feb 19, 2026Updated 8 months ago
- ☆14Dec 9, 2025Updated 10 months ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆15Jul 20, 2026Updated 3 months ago
- A high throughput FFT implementation☆21Jan 17, 2022Updated 4 years ago
- Opensource DDR3 Controller☆497Sep 12, 2026Updated last month
- A hardware-optimized high-quality pseudorandom number generator☆38Jun 6, 2026Updated 4 months ago
- Various FPGA projects targeting a Digilent Arty FPGA board☆11Oct 7, 2020Updated 6 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- Labs for the Ibex Demo System☆18Nov 18, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- example code for the logi-boards from pong chu HDL book☆30Sep 4, 2015Updated 11 years ago
- Verilog Ethernet Switch (layer 2)☆60Oct 18, 2023Updated 3 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆30Mar 24, 2021Updated 5 years ago
- FIFO implementation with different clock domains for read and write.☆17Aug 17, 2021Updated 5 years ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆32Dec 25, 2023Updated 2 years ago
- Project Trellis database☆16Oct 12, 2026Updated 3 weeks ago
- UW reference flow for Free45PDK and The OpenROAD Project☆14Jun 5, 2020Updated 6 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆19Apr 13, 2022Updated 4 years ago
- audio DSP applications using zynq/zed boards☆24Jul 24, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This repository contains Design files for Various Base board Designed for Avnet Zynq Ultrascale+ FPGA SOC☆25Jun 21, 2025Updated last year
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated last month
- Experimental Xilinx Artix-7 driven Data Center Security Communication Module☆72Dec 11, 2025Updated 10 months ago
- Experiments with Marsohod3GW board with Gowin FPGA chip☆20May 8, 2025Updated last year
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- LightWeight IP Application Examples for Xilinx FPGA☆16Jan 19, 2016Updated 10 years ago
- Pipelined RISC-V RV32I Core in Verilog☆43Apr 9, 2023Updated 3 years ago
- The ultimate VCD files comparator☆13May 7, 2020Updated 6 years ago
- Repo for reverse engineering the Hantek 6254BD USB-connected oscilloscope☆14Jul 21, 2019Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- APB master and slave developed in RTL.☆33Oct 25, 2025Updated last year
- A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sit…☆28May 27, 2024Updated 2 years ago
- Docs for the uBld.it Fiddy Plus FT2232H Board☆11Apr 16, 2021Updated 5 years ago
- practice configure AHB-Lite bus protocol☆20Mar 11, 2019Updated 7 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆12Jan 23, 2026Updated 9 months ago
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 5 years ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 5 years ago