Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
☆85Mar 21, 2026Updated 3 months ago
Alternatives and similar repositories for MicroBlaze-DDR3-tutorial
Users that are interested in MicroBlaze-DDR3-tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.☆40Apr 4, 2026Updated 2 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 7 months ago
- Labs for the Ibex Demo System☆18Nov 18, 2023Updated 2 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- Experimental Xilinx Artix-7 driven Data Center Security Communication Module☆68Dec 11, 2025Updated 6 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Apr 26, 2026Updated 2 months ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆23Updated this week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 4 years ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- UART models for cocotb☆35Sep 7, 2025Updated 9 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆55Dec 6, 2023Updated 2 years ago
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆36Jan 28, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated last year
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆30Mar 24, 2021Updated 5 years ago
- example code for the logi-boards from pong chu HDL book☆30Sep 4, 2015Updated 10 years ago
- 100道图像处理算法中文版☆14Jul 17, 2020Updated 5 years ago
- ☆21Oct 20, 2025Updated 8 months ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆31Dec 25, 2023Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆46Jun 7, 2017Updated 9 years ago
- DisplayPort IP-core☆87May 8, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆17Jun 14, 2026Updated 2 weeks ago
- ☆10Jul 25, 2022Updated 3 years ago
- Simulator/interpreter for Arm64 machine language☆14Jun 17, 2022Updated 4 years ago
- ☆11Sep 18, 2025Updated 9 months ago
- AXI Stream UART (verilog)☆12Oct 3, 2019Updated 6 years ago
- ☆19May 20, 2026Updated last month
- ☆15Dec 9, 2025Updated 6 months ago
- ☆11Nov 17, 2025Updated 7 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆82Dec 1, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆122Jun 18, 2026Updated last week
- Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.☆23Oct 10, 2021Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆88Oct 6, 2022Updated 3 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- Cours d'introduction à l'assembleur riscV - Introduction course to RiscV assembly in French☆16May 26, 2020Updated 6 years ago
- The macOS V5+ KiCad builder and packager [moved to https://gitlab.com/kicad]☆13Nov 27, 2019Updated 6 years ago