iscas-tis / riscv-spec-core
Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
☆13Updated 3 weeks ago
Alternatives and similar repositories for riscv-spec-core:
Users that are interested in riscv-spec-core are comparing it to the libraries listed below
- ☆19Updated 9 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆16Updated this week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 2 months ago
- Formal verification tools for Chisel and RISC-V☆13Updated 10 months ago
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- ☆14Updated last month
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- BTOR2 MLIR project☆25Updated last year
- Code repository for Coppelia tool☆23Updated 4 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆35Updated this week
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆12Updated 2 months ago
- ☆12Updated 10 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated last week
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 3 months ago
- RTLCheck☆21Updated 6 years ago
- ☆18Updated 10 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆27Updated 3 months ago
- ☆33Updated last month
- BOOM's Simulation Accelerator.☆14Updated 3 years ago
- ☆11Updated 3 years ago
- ☆17Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- work in progress, playing around with btor2 in rust☆11Updated 3 months ago
- The 'missing header' for Chisel☆20Updated last month
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 6 months ago
- Testing processors with Random Instruction Generation☆37Updated last month
- A Hardware Pipeline Description Language☆44Updated last year
- ☆13Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last week