iscas-tis / riscv-spec-core
Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
☆13Updated 2 weeks ago
Alternatives and similar repositories for riscv-spec-core:
Users that are interested in riscv-spec-core are comparing it to the libraries listed below
- ☆17Updated 8 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆16Updated 3 weeks ago
- Formal verification tools for Chisel and RISC-V☆14Updated 8 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated 2 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- BTOR2 MLIR project☆25Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 5 months ago
- ☆12Updated 6 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated 2 months ago
- ☆17Updated 9 months ago
- ☆13Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated last week
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 2 months ago
- ☆32Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆30Updated this week
- ☆11Updated 3 years ago
- ☆13Updated 4 years ago
- ☆17Updated 3 years ago
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated 2 months ago
- ☆13Updated last month
- Split large FIRRTL into separated modules for incremental compilation.☆10Updated 3 years ago
- Testing processors with Random Instruction Generation☆35Updated 2 weeks ago
- Hardware Model Checker☆40Updated this week
- CoreIR Symbolic Analyzer☆64Updated 4 years ago
- RISC-V Formal in Chisel☆11Updated 11 months ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago