Soappyooo / pointnet_cuda_evalLinks
UCAS国科大2024课程《GPU架构与编程》大作业1,编写pointnet的cuda推理程序。
☆10Updated 7 months ago
Alternatives and similar repositories for pointnet_cuda_eval
Users that are interested in pointnet_cuda_eval are comparing it to the libraries listed below
Sorting:
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Updated 3 years ago
- 关于移植模型至gemmini的文档☆28Updated 3 years ago
- 一个单发射五级静态流水CPU,采用龙芯32位精简版指令集,支持异常和中断处理,使用AXI总线接口,已集成TLB模块☆14Updated 2 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆19Updated 6 months ago
- 中国科学院大学-C语言编程-五子棋☆13Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆20Updated 11 months ago
- Model LLM inference on single-core dataflow accelerators☆10Updated 4 months ago
- ☆12Updated last year
- 基于FPGA的FFT算法并行优化☆12Updated last year
- Accelerate multihead attention transformer model using HLS for FPGA☆11Updated last year
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆23Updated last year
- Vitis 部署加速器工作流介绍☆10Updated 6 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 3 months ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆22Updated 2 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆29Updated 5 years ago
- 中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业☆16Updated 3 years ago
- 中国科学院大学2022秋季学期智能计算系统实验-陈云霁☆10Updated 2 years ago
- ☆24Updated last month
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆29Updated 3 years ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆26Updated 5 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 6 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆84Updated 2 months ago
- gem5 FS模式实验手册☆43Updated 2 years ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- 基4booth乘法器设计与验证☆12Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆41Updated last year
- eyeriss-chisel3☆41Updated 3 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆8Updated 3 years ago