Soappyooo / pointnet_cuda_evalLinks
UCAS国科大2024课程《GPU架构与编程》大作业1,编写pointnet的cuda推理程序。
☆20Updated 11 months ago
Alternatives and similar repositories for pointnet_cuda_eval
Users that are interested in pointnet_cuda_eval are comparing it to the libraries listed below
Sorting:
- 一个单发射五级静态流水CPU,采用龙芯32位精简版指令集,支持异常和中断处理,使用AXI总线接口,已集成TLB模块☆16Updated 2 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆28Updated last year
- 中国科学院大学2022秋季学期智能计算系统实验-陈云霁☆11Updated 2 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆29Updated 4 years ago
- 中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业☆16Updated 3 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Updated 4 years ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆30Updated 9 months ago
- 中国科学院大学-C语言编程-五子棋☆14Updated last year
- A 5-level pipelined MIPS CPU with branch prediction and great cache.☆20Updated 4 years ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆48Updated 3 years ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Updated 3 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆30Updated 5 years ago
- NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖☆10Updated last year
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆25Updated 3 years ago
- 重庆大学计算机学院2018级计算机体系结构cache设计☆11Updated 4 years ago
- ☆84Updated 6 months ago
- ☆20Updated last year
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated last year
- Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU☆14Updated 3 years ago
- A fork of Xiangshan for AI☆33Updated 2 weeks ago
- ☆16Updated last year
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated last year
- "aura" my super-scalar O3 cpu core☆24Updated last year
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆61Updated last year
- ☆16Updated 9 months ago
- 2022龙芯杯个人赛三等奖作品☆14Updated 2 years ago
- A framework for ysyx flow☆12Updated last year
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆15Updated 4 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆79Updated 7 months ago