Alternatives and similar repositories for stt

Users that are interested in stt are comparing it to the libraries listed below

• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆61Updated 5 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆24Updated last year
• eepalms / gem5-newcache
  New Cache implementation using Gem5
  ☆13Updated 11 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 6 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆30Updated 3 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆27Updated 5 months ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆34Updated 5 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• efeslab / dolma
  ☆13Updated 4 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆23Updated 4 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆22Updated 4 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆50Updated 6 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆67Updated 6 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• darchr / parsec-benchmark
  ☆17Updated 4 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆20Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 2 months ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• PittECEArch / AdversarialPrefetch
  ☆20Updated 3 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆23Updated 3 years ago
• aakahlow / gem5Valid_Haswell
  ☆20Updated 5 years ago
• Yujie-Cui / WB-channels
  ☆13Updated 3 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆14Updated 2 years ago
• darchr / gem5-skylake-config
  gem5 configuration for intel's skylake micro-architecture
  ☆52Updated 3 years ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆91Updated 4 years ago
• umd-memsys / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆13Updated 5 years ago
• vusec / tlbdr
  ☆17Updated 3 years ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆140Updated 2 years ago