ilya-sotnikov / riscv-asm-spike
Bare metal RISC-V assembly examples for Spike (no pk)
☆12Updated last year
Related projects ⓘ
Alternatives and complementary repositories for riscv-asm-spike
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Another size-optimized RISC-V CPU for your consideration.☆47Updated this week
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆14Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Wishbone interconnect utilities☆37Updated 5 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A padring generator for ASICs☆22Updated last year
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆94Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- Dual-issue RV64IM processor for fun & learning☆57Updated last year
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆22Updated last year
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- Documenting the Lattice ECP5 bit-stream format.☆51Updated last year
- Tiny tips for Colorlight i5 FPGA board☆55Updated 3 years ago
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆25Updated 3 years ago
- A pipelined RISC-V processor☆47Updated 11 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆17Updated 2 years ago
- A simple three-stage RISC-V CPU☆21Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- Spen's Official OpenOCD Mirror☆48Updated 8 months ago
- FLIX-V: FPGA, Linux and RISC-V☆41Updated last year
- Portable HyperRAM controller☆48Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- ☆29Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- Another tiny RISC-V implementation☆52Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆58Updated 3 years ago