Alternatives and similar repositories for KianV_rv32ia_uLinux_SoC

Users that are interested in KianV_rv32ia_uLinux_SoC are comparing it to the libraries listed below

• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 2 months ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆27Updated 4 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆94Updated 2 weeks ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 4 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆41Updated 2 weeks ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 7 months ago
• MichaelBell / tinyQV
  A Risc-V SoC for Tiny Tapeout
  ☆19Updated 3 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆66Updated last week
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• aignacio / nox
  RISC-V Nox core
  ☆64Updated 3 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆44Updated 4 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆55Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last month
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆28Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆42Updated 4 years ago
• MichaelBell / nanoV
  RISC-V RV32E core designed for minimal area
  ☆16Updated 7 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 5 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆61Updated this week
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆85Updated this week
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆42Updated last year
• Juninho99 / FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera
  Master-thesis-final
  ☆19Updated last year
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆30Updated 6 months ago
• OLIMEX / GateMateA1-EVB
  Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040
  ☆29Updated 6 months ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago