Alternatives and similar repositories for riscv-none-gcc-build

Users that are interested in riscv-none-gcc-build are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 5 years ago
• shenyaming / riscv-fpga
  Share JTAG chain within RISCV core and Xilinx FPGA.
  ☆9Updated 5 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• ucb-bar / chisel-awl
  ☆14Updated 4 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆36Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 4 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 10 months ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆13Updated 8 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆12Updated 2 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 4 months ago
• ucb-bar / midas-examples
  Simple MIDAS Examples
  ☆12Updated 6 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 3 weeks ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆38Updated this week
• fpgadeveloper / ethernet-fmc-max-throughput
  Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput
  ☆11Updated 6 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 5 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 2 years ago