Alternatives and similar repositories for xilinx_axidma

Users that are interested in xilinx_axidma are comparing it to the libraries listed below

• Xilinx / device-tree-xlnx
  Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
  ☆221Updated 3 weeks ago
• Xilinx / dma_ip_drivers
  Xilinx QDMA IP Drivers
  ☆737Updated 2 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆850Updated last year
• Digilent / vivado-library
  ☆646Updated 3 months ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆275Updated 10 months ago
• Xilinx / embeddedsw
  Xilinx Embedded Software (embeddedsw) Development
  ☆1,101Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆840Updated 8 months ago
• corna / xilinx_axidma
  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…
  ☆15Updated 7 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆514Updated 8 months ago
• Xilinx-Wiki-Projects / software-prototypes
  ☆73Updated 4 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆656Updated 8 months ago
• Xilinx / u-boot-xlnx
  The official Xilinx u-boot repository
  ☆643Updated last week
• aquaxis / IPCORE
  ☆141Updated 10 years ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated this week
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,774Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆841Updated 4 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆459Updated last week
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆77Updated 8 months ago
• bmartini / zynq-xdma
  Linux Driver for the Zynq FPGA DMA engine
  ☆90Updated 10 years ago
• Xilinx / XilinxBoardStore
  ☆306Updated this week
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆258Updated this week
• Xilinx / Embedded-Design-Tutorials
  ☆150Updated 2 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆388Updated 2 months ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆232Updated last year
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,453Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆240Updated last year
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆713Updated 2 years ago
• fpgasystems / fpga-network-stack
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆870Updated 4 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆234Updated 3 months ago
• Xilinx / linux-xlnx
  The official Linux kernel from Xilinx
  ☆1,486Updated last week