Alternatives and similar repositories for Zedboard-DMA:

Users that are interested in Zedboard-DMA are comparing it to the libraries listed below

• farbius / dsp_xilinx_ip
  Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python
  ☆32Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆32Updated this week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆56Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• fpgadeveloper / zedboard-axi-dma
  Demonstration of the AXI DMA engine on the ZedBoard
  ☆51Updated 3 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆37Updated 5 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆30Updated 4 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆100Updated last year
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆94Updated 2 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆28Updated 9 months ago
• frobino / axi_custom_ip_tb
  A testbench for an axi lite custom IP
  ☆23Updated 10 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆22Updated 6 months ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆47Updated 2 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆34Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated 3 weeks ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆30Updated 3 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 3 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆62Updated last year
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆55Updated 3 years ago
• Digilent / Zybo-hdmi-in
  ☆12Updated 7 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• efard / DSPHDL
  ☆40Updated 11 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆125Updated 2 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆58Updated 2 years ago