Alternatives and similar repositories for PYNQ4Zybo:

Users that are interested in PYNQ4Zybo are comparing it to the libraries listed below

• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆43Updated 7 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆61Updated 2 years ago
• gtjennings1 / JPEG_Encoder
  ☆15Updated 6 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆38Updated 4 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆71Updated 10 months ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 11 months ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated 2 months ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆34Updated 3 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆14Updated 10 years ago
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆23Updated 11 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆73Updated 2 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• vinodpa / OpenProjects
  ☆24Updated last year
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago