Alternatives and similar repositories for vivado-on-silicon-mac:

Users that are interested in vivado-on-silicon-mac are comparing it to the libraries listed below

• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆976Updated this week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆228Updated 9 months ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆536Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆395Updated 5 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆312Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆582Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆371Updated 2 months ago
• Digilent / vivado-boards
  ☆421Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆459Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆597Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆429Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆273Updated last week
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆375Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆317Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆523Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆600Updated last month
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆158Updated this week
• dalance / svlint
  SystemVerilog linter
  ☆334Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆238Updated 3 weeks ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆197Updated last month
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆388Updated 2 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆661Updated last week
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆276Updated last week
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆555Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆556Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆177Updated 3 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆371Updated 2 weeks ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆427Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆762Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆645Updated 3 months ago