Alternatives and similar repositories for vivado-on-silicon-mac

Users that are interested in vivado-on-silicon-mac are comparing it to the libraries listed below

• lowRISC / style-guides
  lowRISC Style Guides
  ☆441Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆648Updated 3 weeks ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆290Updated last month
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆626Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆364Updated last month
• Digilent / vivado-boards
  ☆450Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆675Updated 2 weeks ago
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆598Updated 8 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,108Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆590Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆635Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆712Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆397Updated 6 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆399Updated this week
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆105Updated 9 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆393Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆441Updated last week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆494Updated 3 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆658Updated 2 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆944Updated this week
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆211Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆510Updated 5 months ago
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆574Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆172Updated this week
• rggen / rggen
  Code generation tool for control and status registers
  ☆406Updated last month
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆302Updated 2 months ago