Alternatives and similar repositories for rv64core

Users that are interested in rv64core are comparing it to the libraries listed below

• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆76Updated this week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• olofk / corescore
  CoreScore
  ☆162Updated 2 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆128Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆156Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• riscv-software-src / riscv-unified-db
  Machine-readable database of the RISC-V specification, and tools to generate various views
  ☆100Updated this week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• mosscomp / moss
  A computer for human beings.
  ☆45Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆175Updated this week
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆114Updated 3 years ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 2 weeks ago
• ultraembedded / riscv32_linux_from_scratch
  RISC-V 32-bit Linux From Scratch
  ☆34Updated 5 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 10 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 3 months ago
• SpinalHDL / NaxRiscv
  ☆295Updated 3 weeks ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆276Updated last week
• riscv-software-src / riscof
  ☆88Updated 5 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆289Updated 6 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 10 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated last month
• bsc-loca / sargantana
  ☆107Updated 2 weeks ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 10 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆112Updated this week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 5 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆26Updated 3 weeks ago