Alternatives and similar repositories for rv64core

Users that are interested in rv64core are comparing it to the libraries listed below

• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆82Updated last week
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆63Updated last week
• ultraembedded / riscv32_linux_from_scratch
  RISC-V 32-bit Linux From Scratch
  ☆35Updated 5 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• olofk / corescore
  CoreScore
  ☆163Updated 2 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆136Updated last week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆93Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆182Updated 2 weeks ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• riscv-software-src / riscv-unified-db
  Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
  ☆106Updated last week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 4 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 2 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated 11 months ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated last month
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆153Updated this week
• bsc-loca / sargantana
  ☆108Updated last month
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago