hex-five / multizone-fpga
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkele…
☆29Updated last year
Alternatives and similar repositories for multizone-fpga:
Users that are interested in multizone-fpga are comparing it to the libraries listed below
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- ☆17Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- RISC-V Formal Verification Framework☆137Updated this week
- Lipsi: Probably the Smallest Processor in the World☆84Updated last year
- AIA IP compliant with the RISC-V AIA spec☆40Updated 3 months ago
- RISC-V Nexus Trace TG documentation and reference code☆50Updated 4 months ago
- ☆86Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆89Updated last month
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last week
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆32Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- ☆46Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated last month
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆53Updated last week
- ☆81Updated last year
- A bare-metal application to test specific features of the risc-v hypervisor extension☆39Updated last year
- SoftCPU/SoC engine-V☆54Updated last month
- RISC-V IOMMU Specification☆114Updated 2 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago