hex-five / multizone-fpgaLinks
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkele…
☆30Updated last year
Alternatives and similar repositories for multizone-fpga
Users that are interested in multizone-fpga are comparing it to the libraries listed below
Sorting:
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆54Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RISC-V Formal Verification Framework☆141Updated last week
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- Testing processors with Random Instruction Generation☆38Updated 2 weeks ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 3 weeks ago
- Platform Level Interrupt Controller☆41Updated last year
- RISC-V Virtual Prototype☆43Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- ☆86Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆56Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago